In recent years, the reduction of power consumption has become a big issue for various kinds of electronic devices represented by mobile terminals as they offer more functions and higher performances, increasing the number of circuits meanwhile the demand for small and light devices also increases. Voltage comparator circuit is widely used as functional circuit block of various kinds of electronics devices. Especially, it is often used in a circuit that converts an analog signal into a digital signal i.e., analog-to-digital converter circuit. Reducing the power consumption of such a voltage comparator circuit is also an issue and it has been performed by some special circuit designs.
For instance, a voltage comparator circuit with low power consumption is disclosed in Patent Document 1. This circuit is constituted by a voltage comparator circuit comprising double flip-flop circuits (double latch-type) shown in FIG. 7. Hereinafter, this circuit will be described in detail.
In FIG. 7, the voltage comparator circuit comprises a first flip-flop circuit constituted by a pair of cross-connected n-type field effect transistors (FET hereinafter) Q103 and Q104, n-type FET Q101 whose source and drain are connected to source and drain of FET Q103 respectively, and, n-type FET Q102 whose source and drain are connected to source and drain of FET Q104 respectively. It also comprises a second flip-flop circuit constituted by a pair of cross-connected p-type FETs Q105 and Q106 with a different polarity from that of the first flip-flop circuit, p-type FET Q107 whose source and drain are connected to source and drain of FET Q105 respectively, p-type FET Q108 whose source and drain are connected to source and drain of FET Q106 respectively, and n-type FETs Q109 and Q110 whose source and drain are connected between the drain of the FETs Q103 and Q104 and the drain of the FETs Q105 and Q106 respectively. The gates of FETs Q107, Q108, Q109 and Q110 are connected in common, to which a pulse signal (strobe signal) φ is supplied. The gates of the FETs Q101 and Q102 are connected to signal input terminals IN1 and IN2 respectively and voltages to be compared are inputted. Furthermore, the drains of the FETs Q109 and Q110 are connected to output terminals OUT2 and OUT1 respectively. The source of the FETs Q101, Q102, Q103, and Q104 are connected to a low-potential power supply VSS, and the source of the FETs Q105, Q106, Q107, and Q108 are connected to a high-potential power supply VDD.
The operation of the voltage comparator circuit with the structure as described above will be explained. In this circuit, the pulse signal φ starts with a low level (the potential of the power supply VSS) first. In the case where the voltage of the power supply VDD is 5V and the threshold voltage of the n-type FET is 0.8V, the circuit will operate at its highest speed if an input voltage is approximately 1V higher than the threshold voltage of the FETs Q101 and Q102. The following explanation will be given assuming the above conditions. Since the FETs Q101 and Q102 are conducted, the drain voltage of the FETs Q103 and Q104 is zero (the potential of the power supply VSS), and since the FETs Q109 and Q110 are not conducted and the FETs Q107 and Q108 are conducted, the potentials of the output terminals OUT1 and OUT2 are equal to the voltage of the power supply VDD (high level).
Next, if a pulse that makes the pulse signal φ high level (the potential of the power supply VDD) is applied, the FETs Q109 and Q110 will be conducted, the FETs Q107 and Q108 will not be conducted, and a current will flow into the flip-flop circuit of the FETs Q103 and Q104 via the FETs Q109 and Q110. At this time, if the potential of the input signal terminal IN1 is higher than that of the input signal terminal IN2, more current will flow in the FET Q101 than in the FET Q102. No drain current will flow in the FETs Q103 and Q104 until the drain potential of either the FET Q103 or FET Q104 exceeds the threshold voltage. When the FETs Q109 and Q110 are conducted, at first, both the drain of the FET Q103 and the drain of the FET Q104 are similarly charged, however, the drain of the FET Q104 (the gate of the FET Q103) exceeds the threshold voltage first since the drain of the FET Q103 has a greater amount of discharge. Then, the FET Q103 starts to discharge, and the potential of the drain of the FET Q103 (the gate of the FET Q104) does not increase. Therefore, the potential of the drain of the FET Q104 continues to increase. Because of this, more current flows in the FET Q109 than in the FET Q110. Then, the flip-flop circuit of the FET Q105 and Q106 operates since the potential of the output terminal OUT2 gets lower than that of the output terminal OUT1, and the potential of the output terminal OUT2 decreases rapidly. As described above, the state of the output terminal is determined according to the potential of the input terminal.
As described, the voltage comparator circuit is constituted by double flip-flop circuits and it has high-speed operation in terms of determining the output condition. Further, since it has a complete symmetrical structure from the input to output, it eliminates the cause of offset voltage, and because power supply noise is applied to the both input voltages, it is canceled out thus eliminating the possibility of malfunctioning due to noise. Furthermore, since it does not consume any current in the initial state (the pulse signal φ is at a low level) and it only consumes a small amount of current during the operation of comparison (the pulse signal φ is at a high level), a voltage comparator circuit with low power consumption can be realized.
Also, another voltage comparator circuit with low power consumption is described in Non-Patent Document 1. This circuit has a structure nearly identical to that of the voltage comparator circuit described in Patent Document 1 except that its input stage is constituted by differential amplifiers of p-type FETs.
[Patent Document 1]
Japanese Patent Kokoku Publication No. JP-02-34490-B2 (FIG. 4)
[Non-Patent Document 1]
G. M. Yin et al., “A High-Speed CMOS Comparator with 8-b Resolution,” (USA), IEEE Journal of Solid-State Circuits, Vol. 27, No. 2, February 1992, pp. 208-211.